cs501 GDB 2016 Solution

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Solved  By : Tahir Siddiqui(Mani)

BC-140201235@Vu.edu.pk

 

Cs501 GDB solution

Device wishing to perform DMA asserts the processors bus request signal.
Processor completes the current bus cycle and then asserts the bus grant signal to the device.
The device then asserts the bus grant ack signal.
The processor senses in the change in the state of bus grant ack signal and starts listening to the data and address bus for DMA activity.
The DMA device performs the transfer from the source to destination address.
During these transfers, the processor monitors the addresses on the bus and checks if any location modified during DMA operations is cached in the processor. If the processor detects a cached address on the bus, it can take one of the two actions:
Processor invalidates the internal cache entry for the address involved in DMA write operation
Processor updates the internal cache when a DMA write is detected
Once the DMA operations have been completed, the device releases the bus by asserting the bus release signal.
Processor acknowledges the bus release and resumes its bus cycles from the point it left off.